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MC34067, MC33067 High Performance Resonant Mode Controllers
The MC34067/MC33067 are high performance zero voltage switch resonant mode controllers designed for off-line and dc-to-dc converter applications that utilize frequency modulated constant off-time or constant deadtime control. These integrated circuits feature a variable frequency oscillator, a precise retriggerable one-shot timer, temperature compensated reference, high gain wide bandwidth error amplifier, steering flip-flop, and dual high current totem pole outputs ideally suited for driving power MOSFETs. Also included are protective features consisting of a high speed fault comparator and latch, programmable soft-start circuitry, input undervoltage lockout with selectable thresholds, and reference undervoltage lockout. These devices are available in dual-in-line and surface mount packages.
Features
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16 16 1 PDIP-16 P SUFFIX CASE 648 1 MC3x067P AWLYYWWG
* Zero Voltage Switch Resonant Mode Operation * Variable Frequency Oscillator with a Control Range * * * * * * * * *
Exceeding 1000:1 Precision One-Shot Timer for Controlled Off-Time Internally Trimmed Bandgap Reference 4.0 MHz Error Amplifier Dual High Current Totem Pole Outputs Selectable Undervoltage Lockout Thresholds with Hysteresis Enable Input Programmable Soft-Start Circuitry Low Startup Current for Off-Line Operation Pb-Free Packages are Available*
VCC 15 VCC UVLO / Enable Variable Frequency Oscillator 5.0 V Reference Vref UVLO 14 One-Shot 2.5 V Clamp Steering Flip-Flop 5 Vref
16 16 1 SOIC-16W DW SUFFIX CASE 751G x A WL YY WW G MC3x067DW AWLYYWWG
1
Enable / 9 UVLO Adjust 1 OSC Charge 2 OSC RC Oscillator 3 Control Current One-Shot 16
= 3 or 4 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
Output A
OSC Charge 1 OSC RC 2
16 One-Shot RC 15 VCC 14 Drive Output A 13 Power GND 12 Drive Output B 11 CSoft-Start 10 Fault Input Enable/UVLO 9 Adjust (Top View)
12 13
Error Amp 6 Output Noninverting 8 Input Inverting Input 7 Soft-Start 11
Output B Pwr GND
OSC Control Current 3 GND 4 Vref 5 Error Amp Out 6
Error Amp
Soft-Start
Fault Detector/ Latch
10
Fault Input
Inverting Input 7 Noninverting Input 8
4
Ground
Figure 1. Simplified Block Diagram
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
1
October, 2005 - Rev. 11
Publication Order Number: MC34067/D
MC34067, MC33067
MAXIMUM RATINGS
Rating Power Supply Voltage Drive Output Current, Source or Sink (Note 1) - Continuous - Pulsed (0.5 ms, 25% Duty Cycle Error Amplifier, Fault, One-Shot, Oscillator and Soft-Start Inputs UVLO Adjust Input Power Dissipation and Thermal Characteristics DW Suffix, Plastic Package, Case 751G TA = 25C Thermal Resistance, Junction-to-Air P Suffix, Plastic Package, Case 648 TA = 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature MC34067 MC33067 Storage Temperature Symbol VCC IO 0.3 1.5 Vin Vin(UVLO) - 1.0 to + 6.0 - 1.0 to VCC V V Value 20 Unit V A
PD RqJA PD RqJA TJ TA
862 145 1.25 100 + 150 0 to + 70 - 40 to + 85
mW C/W W C/W C C
Tstg
- 55 to + 150
C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device MC33067DW MC33067DWG MC33067DWR2 MC33067DWR2G MC33067P MC33067PG MC34067DW MC34067DWG MC34067DWR2 MC34067DWR2G MC34067P MC34067PG Package SOIC-16W SOIC-16W (Pb-Free) SOIC-16W SOIC-16W (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) SOIC-16W SOIC-16W (Pb-Free) SOIC-16W SOIC-16W (Pb-Free) PDIP-16 PDIP-16 (Pb-Free) Shipping 47 Units / Rail 47 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 25 Units / Rail 25 Units / Rail 47 Units / Rail 47 Units / Rail 1000 / Tape & Reel 1000 / Tape & Reel 25 Units / Rail 25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC34067, MC33067
ELECTRICAL CHARACTERISTICS
(VCC = 12 V [Note 2], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF, RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies (Note 3), unless otherwise noted.) Characteristic REFERENCE SECTION Reference Output Voltage (IO = 0 mA, TJ = 25C) Line Regulation (VCC = 10 V to 18 V) Load Regulation (IO = 0 mA to 10 mA) Total Output Variation Over Line, Load, and Temperature Output Short Circuit Current (0C to 70C) (-40C to 85C) Reference Undervoltage Lockout Threshold ERROR AMPLIFIER Input Offset Voltage (VCM = 1.5 V) Input Bias Current (VCM = 1.5 V) Input Offset Current (VCM = 1.5 V) Open Loop Voltage Gain (VCM = 1.5 V, VO = 2.0 V) Gain Bandwidth Product (f = 100 kHz) TA = 25C TA = Tlow to Thigh Input Common Mode Rejection Ratio (VCM = 1.5 V to 5.0 V) Power Supply Rejection Ratio (VCC = 10 V to 18 V, f = 120 Hz) Output Voltage Swing High State (Isource = 2.0 mA) Low State (Isink = 4.0 mA) 1. 2. 3. 4. VIO IIB IIO AVOL GBW 3.0 2.7 CMR PSR VOH VOL 70 80 2.8 - 5.0 - 95 100 3.2 0.6 - - - - - 0.8 dB dB V - - - 70 1.0 0.2 0 100 10 1.0 0.5 - mV mA mA dB MHz Vref Regline Regload Vref IO 30 25 Vth 3.8 100 100 4.3 190 225 4.8 V 5.0 - - 4.9 5.1 1.0 1.0 - 5.2 20 20 5.3 V mV mV V mA Symbol Min Typ Max Unit
Maximum package power dissipation limits must be observed. Adjust VCC above the Startup Threshold voltage before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34067 = - 40C for MC33067 Thigh = + 70C for MC34067 = + 85C for MC33067
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ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V [Note 6], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF,
RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies (Note 7), unless otherwise noted.) Characteristic OSCILLATOR Frequency (Error Amp Output Low) Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) Frequency (Error Amp Output High) Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) Oscillator Control Input Voltage, Pin 3 ONE-SHOT Drive Output Off-Time TA = 25C Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh) DRIVE OUTPUTS Output Voltage Low State (ISink = 20 mA) Low State (ISink = 200 mA) High State (ISource = 20 mA) High State (ISource = 200 mA) Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA) Output Voltage Rise Time (CL = 1.0 nF) Output Voltage Fall Time (CL = 1.0 nF) FAULT COMPARATOR Input Threshold Input Bias Current (VPin 10 = 0 V) Propagation Delay to Drive Outputs (100 mV Overdrive) SOFT-START Capacitor Charge Current (VPin 11 = 2.5 V) Capacitor Discharge Current (VPin 11 = 2.5 V) UNDERVOLTAGE LOCKOUT Startup Threshold, VCC Increasing Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to VCC Minimum Operating Voltage After Turn-On, VCC Decreasing Enable/UVLO Adjust Pin Open Enable/UVLO Adjust Pin Connected to VCC Enable/UVLO Adjust Shutdown Threshold Voltage Enable/UVLO Adjust Input Current (Pin 9 = 0 V) TOTAL DEVICE Power Supply Current (Enable/UVLO Adjust Pin Open) Startup (VCC = 13.5 V) Operating (fOSC = 500 kHz) (Note 6) 5. 6. 7. 8. ICC - - 0.5 27 0.8 35 mA Vth(UVLO) 14.8 8.0 VCC(min) 8.0 7.6 Vth(Enable) Iin(Enable) 6.0 - 9.0 8.6 7.0 - 0.2 10 9.6 - - 1.0 V mA 16 9.0 17.2 10 V V Ichg Idischg 4.5 3.0 9.0 8.0 14 - mA mA Vth IIB tPLH(In/Out) 0.93 - - 1.0 - 2.0 60 1.07 - 10 100 V mA ns V VOL VOH VOL(UVLO) tr tf - - 9.5 9.0 - - - 0.8 1.5 10.3 9.7 0.8 20 15 1.2 2.0 - - 1.2 50 50 V ns ns tBlank 235 225 250 - 270 280 ns kHz fOSC(low) fOSC(high) Vin 490 1850 - 525 2050 2.5 550 kHz 2200 - V Symbol Min Typ Max Unit
Maximum package power dissipation limits must be observed. Adjust VCC above the Startup Threshold voltage before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for MC34067 = - 40C for MC33067 Thigh = + 70C for MC34067 = + 85C for MC33067
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ROSC, OSCILLATOR TIMING RESISTOR (k ) 500 400 300 200 100 0 COSC = 200 pF COSC = 500 pF VCC = 12 V RVFO = RT = CT = 500 pF TA = 25C Oscillator Discharge Time is Measured at the Drive Outputs. 0 40 60 80 tdischg, OSCILLATOR DISCHARGE TIME (ms) 20 100 f OSC , OSCILLATOR FREQUENCY (kHz) COSC = 300 pF 3500 3000 2500 2000 COSC = 300 pF 1500 1000 500 0 0 400 800 1200 1600 IOSC, OSCILLATOR CONTROL CURRENT (mA) 2000 VCC = 12 V TA = 25C ROSC = 18.2 k
Figure 2. Oscillator Timing Resistor versus Discharge Time
Figure 3. Oscillator Frequency versus Oscillator Control Current
VOL, OUTPUT LOW STATE VOLTAGE (V)
0.35 0.30 0.25 0.20 0.15 0.10 0.05
60 VCC = 12 V COSC = 500 pF ROSC = 100 k TA = 25C CT = 300 pF 10 6.0 One-Shot Period is Measured at the Drive Outputs. 0.3 0.6 1.0 3.0 tOS, ONE-SHOT PERIOD (ms) 6.0 10 CT = 200 pF
RT, TIMING RESISTOR (k )
30 20
CT = 500 pF
0
0.5 1.0 1.5 2.0 2.5 IOSC, OSCILLATOR CONTROL CURRENT (mA)
3.0
3.0 0.1
Figure 4. Error Amp Output Low State Voltage versus Oscillator Control Current
Figure 5. One-Shot Timing Resistor versus Period
50 40 30 20 10 0 -10 10 k Phase Phase Margin = 64 100 k 1.0M f, FREQUENCY (Hz) 10M Gain VCC = 12 V VO = 2.0 V RL = 100 k TA = 25C
50 0, EXCESS PHASE (DEGREES) 60 70 80 90 100 110 120
V ref, REFERENCE OUTPUT VOLTAGE CHANGE (mV)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
0
*Vref = 5.0 V
- 10 - 20 - 30 - 40 - 50 - 55 *Vref = 5.2 V - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) 100 125
*Vref = 5.1 V
VCC = 12 V RL = *Vref at TA = 25C
- 20
Figure 6. Open Loop Voltage Gain and Phase versus Frequency
Figure 7. Reference Output Voltage Change versus Temperature
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MC34067, MC33067
V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)
V sat , OUTPUT SATURATION VOLTAGE (V)
0 TA = - 40C -10 - 20 - 30 - 40 - 50 VCC = 12 V TA = - 20C TA = -125C
0 -1.0 VCC TA = 25C TA = - 40C Source Saturation (Load to Ground) VCC = 12 V 80 ms Pulsed Load 120 Hz Rate
- 2.0 - 3.0 3.0 2.0 1.0 0 0
TA = - 40C TA = 25C Source Saturation (Load to VCC) 0.2 GND 1.0
0
20 40 60 80 Iref, REFERENCE SOURCE CURRENT (mA)
100
0.4 0.6 0.8 IO, OUTPUT LOAD CURRENT (A)
V OL , SOFT-START SATURATION VOLTAGE (V)
f, OPERATING FREQUENCY (kHz)
I CC, SUPPLY CURRENT (mA)
90% 10% 2000 1600 1200 800 400 0 30
Figure 8. Reference Output Voltage Change versus Source Current
Figure 9. Drive Output Saturation Voltage versus Load Current
3.2
CL = 1.0 nF TA = 25 C
2.4
1.6
0.8
VCC = 12 V Pin 10 = Vref TA = 25 C 0 2.0 4.0 6.0 8.0 Idchg, CAPACITOR DISCHARGE CURRENT (mA) 10
0
20 ns/DIV
Figure 10. Drive Output Waveform
Figure 11. Soft-Start Saturation Voltage versus Capacitor Discharge Current
24 VCC = 12 V CL = 1.0 nF TA = 25 C 20 16 12 8.0 4.0 0 0
TA = 25 C
Enable/UVLO Adjust Pin Open (Solid Line) Enable/UVLO Adjust Pin to VCC (Dashed Line) 4.0 8.0 12 VCC, SUPPLY VOLTAGE (V) 16 20
40
50 60 70 ICC, SUPPLY CURRENT (mA)
80
90
Figure 12. Operating Frequency versus Supply Current
Figure 13. Supply Current versus Supply Voltage
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MC34067, MC33067
VCC 15
50k Enable / UVLO Adjust 7.0k 9 50k 8.0 V
7.0k 5.1 V Reference Vref 5 Vref UVLO 4.2/4.0 V Vref
VCC UVLO
Vref OSC Charge 1 ROSC COSC One-Shot RC CT RT Oscillator 16 Control Current IOSC 3 RVFO One-Shot 3.1V 4.9 V/3.6 V R S OSC RC 2 IOSC 4.9V/3.6 V Oscillator Q1 D1 Q2
14 Steering Flip-Flop Q T RQ
Output A
Power 13 Ground
Output B 12
Fault Comparator Fault Input 10 1.0 V
Error Amp Output 6 8 Noninverting Input Inverting Input 7 Soft-Start 11
Q Error Amp Clamp Error Amp
9.0 mA
Fault Latch
4
Ground
Figure 14. MC34067 Representative Block Diagram
5.1 V COSC 3. 6 V One-Shot 5.1 V 3.6 V
Output A
Output B
tOS
tOS
tOS
tOS
tOS
tOS
High State Error Amp output, minimum IOSC current occurring at minimum input voltage, maximum load.
Low State Error Amp output, maximum IOSC current occurring at maximum input voltage, minimum load.
Figure 15. Timing Diagram
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MC34067, MC33067
OPERATING DESCRIPTION
Introduction
As power supply designers have strived to increase power conversion efficiency and reduce passive component size, high frequency resonant mode power converters have emerged as attractive alternatives to conventional pulse-width modulated control. When compared to pulse-width modulated converters, resonant mode control offers several benefits including lower switching losses, higher efficiency, lower EMI emission, and smaller size. A new integrated circuit has been developed to support this trend in power supply design. The MC34067 Resonant Mode Controller is a high performance bipolar IC dedicated to variable frequency power control at frequencies exceeding 1.0 MHz. This integrated circuit provides the features and performance specifically for zero voltage switching resonant mode power supply applications. The primary purpose of the control chip is to provide a fixed off-time to the gates of external power MOSFETs at a repetition rate regulated by a feedback control loop. Additional features of the IC ensure that system startup and fault conditions are administered in a safe, controlled manner. A simplified block diagram of the IC is shown on the front page, which identifies the main functional blocks and the block-to-block interconnects. Figure 14 is a detailed functional diagram which accurately represents the internal circuitry. The various functions can be divided into two sections. The first section includes the primary control path which produces precise output pulses at the desired frequency. Included in this section are a variable frequency Oscillator, a One-Shot, a pulse Steering Flip-Flop, a pair of power MOSFET Drivers, and a wide bandwidth Error Amplifier. The second section provides several peripheral support functions including a voltage reference, undervoltage lockout, soft-start circuit, and a fault detector.
Primary Control Path
frequencies exceeding 1.0 MHz. The Error Amplifier can control the oscillator frequency over a 1000:1 frequency range, and both the minimum and maximum frequencies are easily and accurately programmed by the proper selection of external components. The functional diagram of the Oscillator and One-Shot timer is shown in Figure 16. The oscillator capacitor (COSC) is initially charged by transistor Q1. When COSC exceeds the 4.9 V upper threshold of the oscillator comparator, the base of Q1 is pulled low allowing COSC to discharge through the external resistor, (ROSC), and the oscillator control current, (IOSC). When the voltage on COSC falls below the 3.6 V lower threshold of the comparator, Q1 turns on and again charges COSC. COSC charges from 3.6 V to 5.1 V in less than 50 ns. The high slew rate of COSC and the propagation delay of the comparator make it difficult to control the peak voltage. This accuracy issue is overcome by clamping the base of Q1 through a diode to a voltage reference. The peak voltage of the oscillator waveform is thereby precisely set at 5.1 V.
VCC OSC Charge 1 ROSC COSC OSC RC 2 One-Shot RC CT RT Oscillator 10 Control Current IOSC 3 RVFO 6 One-Shot 4.9V/3.6V 3.1 V Error Amp Clamp IOSC Oscillator 4.9 V/3.6 V Vref VCC
Q1
D1
Error Amp Output
Figure 16. Oscillator and One-Shot Timer
The output pulse width and repetition rate are regulated through the interaction of the variable frequency Oscillator, One-Shot timer and Error Amplifier. The Oscillator triggers the One-Shot which generates a pulse that is alternately steered to a pair of totem pole output drivers by a toggle Flip-Flop. The Error Amplifier monitors the output of the regulator and modulates the frequency of the Oscillator. High speed Schottky logic is used throughout the primary control channel to minimize delays and enhance high frequency characteristics.
Oscillator
The characteristics of the variable frequency Oscillator are crucial for precise controller performance at high operating frequencies. In addition to triggering the One-Shot timer and initiating the output deadtime, the oscillator also determines the initial voltage for the one-shot capacitor. The Oscillator is designed to operate at
The frequency of the Oscillator is modulated by varying the current flowing out of the Oscillator Control Current (IOSC) pin. The IOSC pin is the output of a voltage regulator. The input of the voltage regulator is tied to the variable frequency oscillator. The discharge current of the Oscillator increases by increasing the current out of the IOSC pin. Resistor RVFO is used in conjunction with the Error Amp output to change the IOSC current. Maximum frequency occurs when the Error Amplifier output is at its low state with a saturation voltage of 0.1 V at 1.0 mA. The minimum oscillator frequency will result when the IOSC current is zero, and COSC is discharged through the external resistor (ROSC). This occurs when the Error Amplifier output is at its high state of 2.5 V. The minimum and maximum oscillator frequencies are programmed by the proper selection of resistor ROSC and RVFO.
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MC34067, MC33067
The minimum frequency is programmed by ROSC using Equation 1:
- tPD t (max) - 70 ns (min) R OSC = = 0.348 C OSC C OSC n 5.1 3.6 where tPD is the internal propagation delay. 1 Error Amplifier
(eq. 1)
A fully accessible high performance Error Amplifier is provided for feedback control of the power supply system. The Error Amplifier is internally compensated and features dc open loop gain greater than 70 dB, input offset voltage of less than 10 mV and a guaranteed minimum gain-bandwidth product of 2.5 MHz. The input common mode range extends from 1.5 V to 5.1 V, which includes the reference voltage.
The maximum oscillator frequency is set by the current through resistor RVFO. The current required to discharge COSC at the maximum oscillator frequency can be calculated by Equation 2:
I (max) = C OSC 5.1 - 3.6 1 (max) = 1.5COSC (max)
(eq. 2)
Oscillator Control Current 3 IOSC RVFO 6 8 Noninverting Input Inverting Input 7 Error Amp 3.1 V
Error Amp Output
Error Amp Clamp
The discharge current through ROSC must also be known and can be calculated by Equation 3:
1 (min) -
IR
OSC
=
5.1 - 3.6 ROSC
-
R OSC COSC
(eq. 3)
1 (min) R OSC COSC
Figure 17. Error Amplifier and Clamp
=
1.5 R OSC
Resistor RVFO can now be calculated by Equation 4:
2.5 - V EAsat RVFO = I(max) - IR OSC One-Shot Timer
(eq. 4)
When the Error Amplifier output is coupled to the IOSC pin by RVFO, as illustrated in Figure 17, it provides the Oscillator Control Current, IOSC. The output swing of the Error Amplifier is restricted by a clamp circuit to improve its transient recovery time.
Output Section
The One-Shot is designed to disable both outputs simultaneously providing a deadtime before either output is enabled. The One-Shot capacitor (CT) is charged concurrently with the oscillator capacitor by transistor Q1, as shown in Figure 16. The one-shot period begins when the oscillator comparator turns off Q1, allowing CT to discharge. The period ends when resistor RT discharges CT to the threshold of the One-Shot comparator. The lower threshold of the One-Shot is 3.6 V. By choosing CT, RT can by solved by Equation 5:
RT = t OS CT n 5.1 3.6 = t OS 0.348 C T
(eq. 5)
The pulse(tOS), generated by the Oscillator and One-Shot timer is gated to dual totem-pole output drives by the Steering Flip-Flop shown in Figure 18. Positive transitions of tOS toggle the Flip-Flop, which causes the pulses to alternate between Output A and Output B. The flip-flop is reset by the undervoltage lockout circuit during startup to guarantee that the first pulse appears at Output A.
VCC
Output A Steering Flip-Flop Q T RQ PWR GND VCC 14 Power Ground 13
Errors in the threshold voltage and propagation delays through the output drivers will affect the One-Shot period. To guarantee accuracy, the output pulse of the control chip is trimmed to within 5% of 250 ns with nominal values of RT and CT. The outputs of the Oscillator and One-Shot comparators are OR'd together to produce the pulse tOS, which drives the Flip-Flop and output drivers. The output pulse (tOS) is initiated by the Oscillator and terminated by the One-Shot comparator. With zero voltage resonant mode converters, the oscillator discharge time should never be set less than the one-shot period.
Output B 12 PWR GND
Figure 18. Steering Flip-Flop and Output Drivers
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The totem-pole output drivers are ideally suited for driving power MOSFETs and are capable of sourcing and sinking 1.5 A. Rise and fall times are typically 20 ns and 15 ns respectfully when driving a 1.0 nF load. High source/sink capability in a totem-pole driver normally increases the risk of high cross conduction current during output transitions. The MC34067 utilizes a unique design that virtually eliminates cross conduction, thus controlling the chip power dissipation at high frequencies. A separate power ground pin is provided to isolate the sensitive analog circuitry from large transient currents.
VCC 15
50k Enable / UVLO Adjust 7.0k 9 50k
7.0k Vref 5.1 V Reference 8.0 V VCC UVLO Vref UVLO Vref 5
UVLO
4.2/4.0 V
Figure 19. Undervoltage Lockout and Reference
PERIPHERAL SUPPORT FUNCTIONS The MC34067 Resonant Controller provides a number of support and protection functions including a precision voltage reference, undervoltage lockout comparators, soft-start circuitry, and a fault detector. These peripheral circuits ensure that the power supply can be turned on and off in a controlled manner and that the system will be quickly disabled when a fault condition occurs.
Undervoltage Lockout and Voltage Reference
to external loads. The reference is trimmed to better than 2% initial accuracy and includes active short circuit protection.
Fault Detection
Separate undervoltage lockout comparators sense the input VCC voltage and the regulated reference voltage as illustrated in Figure 19. When VCC increases to the upper threshold voltage, the VCC UVLO comparator enables the Reference Regulator. After the Vref output of the Reference Regulator rises to 4.2 V, the Vref UVLO comparator switches the UVLO signal to a logic zero state enabling the primary control path. Reducing VCC to the lower threshold voltage causes the VCC UVLO comparator to disable the Reference Regulator. The Vref UVLO comparator then switches the UVLO output to a logic one state disabling the controller. The Enable/UVLO Adjust pin allows the power supply designer to select the VCC UVLO threshold voltages. When this pin is open, the comparator switches the controller on at 16 V and off at 9.0 V. If this pin is connected to the VCC terminal, the upper and lower thresholds are reduced to 9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO Adjust pin low will pull the VCC UVLO comparator input low (through an internal diode) turning off the controller. The Reference Regulator provides a precise 5.1 V reference to internal circuitry and can deliver up to 10 mA
Converter protection from adverse operating conditions can be implemented with proper use of the Fault Comparator and Latch blocks that are illustrated in Figure 20. The Fault Comparator has an input threshold of 1.0 V and when exceeded, sets the Fault Latch and generates two logic signals that simultaneously disable the primary control path. The signal line labeled "Fault" connects directly to two gates that control the output drivers. This direct path reduces the driver turn-off propagation delay to approximately 70 ns. The Fault Latch output is OR'ed with the UVLO output that is derived from the Vref UVLO comparator, to produce the logic output labeled "UVLO+Fault". This signal disables the Oscillator and the One-Shot by forcing both the COSC and CT capacitors to be continually charged. The Fault Latch is automatically reset during startup by a logic "1" that appears at the Vref UVLO comparator output. The latch can also be reset after startup by momentarily pulling the Enable/UVLO Adjust pin low to disable the Reference. Note that after activation, the Fault Latch will remain in a set state only as long as VCC is provided to the MC34067. Also, Drive Output B will assume a high state if the Fault input signal drops below the 1.0 V threshold level even after the Fault Latch has been set. In some applications this characteristic could be problematic but it can be easily remedied by AC coupling Drive Output B.
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UVLO UVLO + Fault R Q 9.0 mA Error Amp Clamp S Fault Latch 1.0 V Fault Comparator Fault Input 10 Fault
Soft-Start Circuit
CSoft-Start 11
Soft-Start Buffer
6
Ground
Figure 20. Fault Detector and Soft-Start
The Soft-Start circuit shown in Figure 20 forces the variable frequency Oscillator to start at the maximum frequency and ramp downward until regulated by the feedback control loop. The external capacitor at the CSoft-Start terminal is initially discharged by the UVLO+Fault signal. The low voltage on the capacitor passes through the Soft-Start Buffer to hold the Error Amplifier output low. After UVLO+Fault switches to a logic zero, the soft-start capacitor is charged by a 9.0 mA current source. The buffer allows the Error Amplifier output to follow the soft-start capacitor until it is regulated by the Error Amplifier inputs. The soft-start function is generally applicable to controllers operating below resonance and can be disabled by simply opening the CSoft-Start terminal.
APPLICATIONS INFORMATION The MC34067 is specifically designed for zero voltage switching (ZVS) quasi-resonant converter (QRC) applications. The IC is optimized for double-ended push-pull or bridge type converters operating in continuous conduction mode. Operation of this type of ZVS with resonant properties is similar to standard push-pull or bridge circuits in that the energy is transferred during the transistor on-time. The difference is that a series resonant tank is usually introduced to shape the voltage across the power transistor prior to turn-on. The resonant tank in this topology is not used to deliver energy to the output as is the case with zero current switch topologies. When the power transistor is enabled the voltage across it should already be zero, yielding minimal switching loss. Figure 21 shows a timing diagram for a half-bridge ZVS QRC. An application circuit is shown in Figure 22. The circuit built is a dc to dc half-bridge converter delivering 75 W to the output from a 48 V source. When building a zero voltage switch (ZVS) circuit, the objective is to waveshape the power transistor's voltage waveform so that the voltage across the transistor is zero when the device is turned on. The purpose of the control IC is to allow a resonant tank to waveshape the voltage across the power transistor while still maintaining regulation. This is accomplished by maintaining a fixed deadtime and by varying the frequency; thus the effective duty cycle is changed. Primary side resonance can be used with ZVS circuits. In the application circuit, the elements that make the resonant tank are the primary leakage inductance of the transformer (LL) and the average output capacitance (COSS) of a power MOSFET (CR). The desired resonant frequency for the application circuit is calculated by Equation 6:
r = 1 2
(eq. 6)
L L 2C R
In the application circuit, the operating voltage is low and the value of COSS versus Drain Voltage is known. Because the COSS of a MOSFET changes with drain voltage, the value of the CR is approximated as the average COSS of the MOSFET. For the application circuit the average COSS can be calculated by Equation 7:
CR = 2 * C OSS measured at 1 V 2 in
(eq. 7)
The MOSFET chosen fixes CR and that LL is adjusted to achieve the desired resonant frequency. However, the desired resonant frequency is less critical than the leakage inductance. Figure 21 shows the primary current ramping toward its peak value during the resonant transition. During this time, there is circulating current flowing through the secondary inductance, which effectively makes the primary inductance appear shorted. Therefore, the current through the primary will ramp to its peak value at a rate controlled by the leakage inductance and the applied voltage. Energy is not transferred to the secondary during this stage, because the primary current has not overcome the circulating current in the secondary. The larger the leakage inductance, the longer it takes for the primary current to slew. The practical effect of this is to lower the duty cycle, thus reducing the operating range.
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11
MC34067, MC33067
The maximum duty cycle is controlled by the leakage inductance, not by the MC34067. The One-Shot in the MC34067 only assures that the power switch is turned on under a zero voltage condition. Adjust the one-shot period
5.1 V COSC 3.6 V 5.1 V One-Shot 3.6 V
so that the output switch is activated while the primary current is slewing but before the current changes polarity. The resonant stage should then be designed to be as long as the time for the primary current to go to 0 A.
Drive Output A
Drive Output B
Vin
Input Voltage
1/2 Vin
0V + Iprimary
Primary Current
0A
- Iprimary Vin/Turns Ratio
Output Rectifier Voltage
Figure 21. Application Timing Diagram
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V CC
10 Vin 36 V to 56 V Reference 5 100 T1 1 1N5819 14 2 13 16 1.0k 12 1N5819 3 100 T3 500pF 51/0.5W 1N5819 x 4 1.0k T2 MTP33N10E 1.0 MBR2535 CTL L1 30 1.0 500pF 51/0.5W
15
9
L2 2 Vout 5.0 V
330pF
18k
100pF
2.7k
1.1k 10k 6 10 470pF 470 220pF 8 7 0.01 4 11
3.9k
1.6k 330pF
1500pF
16k
MC34067, MC33067
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Conditions V in = 40 V to 56 V, IO =15 A V in = 48 V, IO = 10 A to 15 A V in = 48 V, IO = 15 A, fswitch = 1.0 MHz V in = 48 V, IO = 10 A, fswitch = 1.7 MHz V in = 48 V, IO = 15 A, fswitch = 1.0 MHz Results 20 mV = 0.198% 4.0 mV = 0.039% 25 mVp-p 83.5% 84.2%
13
T1 = Primary: 12 turns #48 AWG (1300 strands litz wire) Secondary: 6 turns center tapped #48 AWG (1300 strands litz wire) Core: Philips 3F3 4312 020 4124 Bobbin: Philips 4322 021 3525 Primary Leakage Inductance = 1.0 H T2 = All windings: 8 turns #36 AWG Core: Philips 3F3 EP7-3F3 Bobbin: Philips EP7PCB1-6 T3 = Coilcraft D1870 (100 turns)
Test
Line Regulation
Load Regulation
Output Ripple
Efficiency
L1 = 2 turns #48 AWG (1300 strands litz wire) Core: Philips 3F3 EP10-3F3 Bobbin: Philips EP10PCB1-8 Inductance = 1.8 H L2 = 5 turns #48 AWG (1300 strands litz wire) Core: 0.5 diameter air code Inductance = 100 nH Heatsinks = AAVID Engineering Inc. 533402B02552 with clip MC34067-5803 Insulators = Berquist Sil-Pad 1500
Figure 22. Application Circuit
MC34067, MC33067
(Top View)
(Bottom View) 5.0
3.875
Figure 23. Printed Circuit Board and Component Layout
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14
MC34067, MC33067
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648-08 ISSUE T
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL.
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
DIM A B C D F G H J K L M S
INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040
MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
SOIC-16W DW SUFFIX CASE 751G-03 ISSUE C
D
16 M 9
A
q
h X 45_
0.25
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0_ 7_
H
M
B
8X
1
8
16X
B TA
S
0.25
M
B
S
A
E B
A1
14X
e
SEATING PLANE
T
C
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15
L
MC34067, MC33067
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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16
MC34067/D

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